Qualcomm Snapdragon 835 (MSM8998) APU

Circuit Analysis Report

PLL Block

Images from the report

This report presents a partial circuit analysis of a selected phase locked loop (PLL) block on the Qualcomm MSM8998 SoC. Four similar PLL blocks and one different PLL block can be seen on the MSM8998 die, all with visible spiral inductors and recognizable PLL layout features. The Qualcomm MSM8998 SoC die is manufactured in Samsung 13-metal, single-poly,10nm LPE FinFET process. An added thin film resistor layer is found on the metal 1 layer. The die size is measured 7.84mm by 9.22mm, given an area of 72.30mm² which is a little bit smaller than Apple A11.

This report consists of the hierarchically-organized transistor-level circuit function analysis of the selected PLL block, presented in both pdf format for general review and IC Explorer for crossing circuit-layout review. The IC Explorer outputs industry formats of netlists including SPICE, Verilog, VHDL, and EDIF200 for function verification and performance simulations.

From the report’s design overview:

Schematic 1.0.0 shows the top level diagram of the PLL block of the Qualcomm MSM8998 SoC. The partially analyzed PLL circuits are organized in twelve subcircuits: 2.0.0 CKF Input, 3.0.0 Phase Detector, 4.0.0 Charge Pump, 5.0.0 VCO with LC Tank, 6.0.0 Loop Filter, 7.0.0 Regulator VCO, 8.0.0 Frequency Divider, 9.0.0 Clock Output, 10.0.0 Timer, 11.0.0 Comparator and 12.0.0 Current Generator. The PLL block is located on the I/O area of the Qualcomm MSM8998 SoC die as shown on Page 8 of this report.

The schematic 2.0.0 CKF Input is a buffering circuit for reference input. The digital phase detector in Schematic 3.0.0 is a dual D-type flip flop phase comparator. Delay buffers are used in the reset feedback loop to prevent the dead zone.

The charge pump circuit in Schematic 4.1.0 is connected to two programmable current resources. Schematic 12.0.0 shows one of the programmable current resources which includes a large number of current generator cells (Schematic 12.1.0 and Schematic 12.2.0). A comparator is used for monitoring the charge pump voltage range. An LDO voltage regulator (Schematic 7.2.0) is used to generate a smooth programmable power supply for the LC tank VCO… Unlock the full report

The report includes the full design review.

The report includes interactive schematics for the following subcircuits:

1.0.0 Top Level Diagram
2.0.0 CKF Input
3.0.0 Phase Detector
4.0.0 Charge Pump
5.0.0 VCO with LC Tank
6.0.0 Loop Filter
7.0.0 Regulator VCO
8.0.0 Frequency Divider
9.0.0 Clock Output
10.0.0 Timer
11.0.0 Comparator
12.0.0 Current Generator
Digital Cell Library

The report includes the interactive schematic and layout image database at high-resolution.

Also check out our NVIDIA report:

NVIDIA GP104 GeForce GT1070

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Hierarchically organized schematics and high-resolution layout images
Report delivered with interactive software
Die markings: NVIDIA GP104-A01 2015

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Phase-Lock-Loop (PLL)

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