An I/O Pad of GDDR5X Interface
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NVIDIA GP104 GPU (GeForce GT1070)
Circuit Analysis Report
This report presents a partial circuit analysis of a selected repeating I/O pads on a GDDR5X interface of the GP104 GPU. The GP104 GPU die is made in TSMC 14-metal, 16nm FinFET process with a die size of 19.3mm by 16.4mm.This report consists of the circuit analysis of the selected GDDR5X data I/O pad, organized hierarchically in transistor-level. The report is presented in both pdf format for general review and IC Explorer for crossing circuitlayout review. The IC Explorer can output industry formats of netlists including SPICE, Verilog, VHDL, and EDIF200 for function verification and performance simulations.
From the report’s design overview:
Schematic 1.0.0 shows the top level diagram of the selected GDDR5X high speed DQ I/O circuit on the NVIDIA GP104 GPU die. The partially analyzed circuits are organized in seven subcircuits: Schematic 2.0.0 Clock Circuit, Schematic 3.0.0 Reference Generator, Schematic 4.0.0 Data Input Path, Schematic 5.0.0 Driver with ODT, Schematic 6.0.0 Switch and Schematic 7.0.0 Power Supply Switches.
The schematic 2.0.0 shows clock generating circuits of this DQ I/O pad. Two pairs of processed clock signals are sent to the Schematic 4.0.0 Data Input Path and Schematic 5.0.0 Driver with ODT. An additional pair of processed clock signals are send to the unanalyzed standard-cell digital area that is not far away from the clock generating block.
The Reference Generator in Schematic 3.0.0 is a high accuracy resistor ladder which generates a pair of precise voltages VRH/VRL for data input circuits as references… Unlock the full report
The report includes the full design review.
The report includes interactive schematics for the following subcircuits:
1.0.0 Top Level Diagram
2.0.0 Clock Circuit
3.0.0 Reference Generator
4.0.0 Data Input Path,
5.0.0 Driver with ODT
6.0.0 Switch
7.0.0 Power Supply Switches
The report includes the interactive schematic and layout image database at high-resolution.
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