ClearView Subscription

Floorplan and digital library layout analysis reports targeting the industry’s most important commercial releases


Device identification,
markings and
technical summary

Floorplan analysis
and IP block

Digital library
analysis of CPU and
GPU blocks

Library cell
layout at gate
level and M1

Power switch layout
and memory block

Get timely data on the most important industry events
See clearly into the world’s most complex ICs
Forecast future trends and make better market decisions
Gain a clear view of fin pitch, logic areas and sizes, memory areas, library track heights, gate count as NAND2 cell equivalents, power switch area  efficiency, memory types and bit cell area, including:
  • PCB, package and die images, die markings, gate level die photo
  • Fin Pitch, contacted poly pitch, minimum metal pitch
  • Measured process pitches, functional block areas, logic block summary, sampled area power switch measurements, memory block summary
  • Die architecture, CPU and GPU layout, CPU and GPU area track height, CPU and GPU area cell layout, sampled memory blocks
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A new digital library analysis subscription service from the the team that created the original semiconductor reverse engineering subscription